It is known to form integrated circuit devices (i.e., semiconductors) including a SiGex layer by, for example, patterning. In some conventional approaches, an intermediate SiGex layer is formed between upper and lower layers and is selectively patterned using, for example, an etch mask through which an exposed portion of an integrated circuit substrate is etched. However, it may be difficult to selectively etch the intermediate SiGex layer using only the etch mask. It is known to use lateral etching for predetermined times or to use additional processes to selectively etch the SiGex layer. However, time based etching may be regarded as a very unpredictable approach.
Lateral etching applied to an intermediate layer is discussed, for example, in published U.S. patent application Ser. No. 6,429,091 B1, to Chen et al., entitled “Patterned Buried Insulator.” In particular, Chen et al. discusses laterally removing a buried doping layer via anisotropic etching after forming the buried doping layer by ion implantation. The etching in Chen et al. is carried out on a P-type silicon substrate, and thus, it may be very difficult to etch only the SiGex layer between the Si layers, as there may be patterning effects on the other layers as well.